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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001 Revised May 2001
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output low level is typically less than 0.5V, the output level high is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink -24mA/+24mA s B Port sink +50mA
Ordering Code:
Order Number GTLP10B320MTD Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS500483
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GTLP10B320
Pin Descriptions
Pin Names OEB, OEC Description B Port, C Port Output Enable respectively (Active LOW)
Connection Diagram
VCC, GND, VREF Device Supplies LECLKAB, LECLKBC SEL SAB, SBC B0-B9 A0-A9 C0-C9 VERC A-to-B, B-to-C Latch CLK respectively (Transparent Active HIGH) Selects Internal Feedback Path Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively B Port GTLP I/O A Port LVTTL Inputs C Port LVTTL Outputs Edge Rate Control Pin (GND = Slow Edge Rate) (VCC = Fast Edge Rate)
Functional Description
The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals (LECLKAB and LECLKBC) and output enables (OEB and OEC). The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin. For A-to-B data flow the device is configured into a latch/ transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance.
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GTLP10B320
Functional Tables
I/O Path: SEL = 1 (External Feedback Path) (Note 2) Inputs OEB 0 0 0 0 0 0 0 0 1 OEC 1 1 1 1 1 1 1 1 1 SAB 0 0 0 0 1 1 1 1 X SBC X X X X X X X X X LECLKAB LECLKBC Mode (AB) Register Register Register Register Latch Buffer Latch Buffer High Impedance An L H L H L L H H X Cn X X X X X X X X X Outputs Bn L H B0 (Note 1) B0 (Note 1) L L H H Z

L L
X X X X X X X X X
H
H X
Note 1: Output level before the indicated steady state input conditions were established. Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.
Internal Feedback Path: SEL = 0 (Internal Feedback Path) (Note 3) Inputs OEB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SAB 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 X SBC 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 X LECLKAB LECLKBC Mode (AB/BC) Register/Register Register/Register Register/Register Register/Register Register/Register Register/Register Register/Latch Register/Buffer Register/Latch Register/Buffer Register/Latch Register/Buffer Register/Latch Latch/Register Latch/Register Latch/Register Latch/Register Buffer/Register Buffer/Register Latch/Register Latch/Latch Latch/Latch Buffer/Buffer Buffer/Buffer High Impedance An L H X L H X L L H H X X X L H L H L H X L H L H X Bn L H L H L L H H Outputs Cn L H B0 (Note 4) B0 (Note 4) L L H H

L

L L L
B0 (Note 4) B0 (Note 4)

L
B0 (Note 4) B0 (Note 4)

L L L
H
H
H L
B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) L H L H L H L H L H Z L H B0 (Note 4) B0 (Note 4) L H L H L H Z

H H L

L L

L
B0 (Note 4) B0 (Note 4)

H H X

H H X
Note 3: Function identical for SEL = 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port. Note 4: Output level before the indicated steady state input conditions were established.
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GTLP10B320
Logic Diagram
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GTLP10B320
Absolute Maximum Ratings(Note 5)
Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 6) DC Output Sink Current into C Port IOL DC Output Source Current from C Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V ESD Rating Storage Temperature (TSTG) 100 mA 48 mA
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V
Recommended Operating Conditions
Supply Voltage VCC Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins HIGH Level Output Current (IOH) C Port LOW Level Output Current (IOL) C Port B Port Operating Temperature (TA) 0.0V to VCC 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V
-48 mA
-24 mA +24 mA +50 mA -40C to +85C
-50 mA -50 mA >2000V -65C to +150C
Note 5: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VTT VIK VOH C Port B Port Others B Port Others B Port B Port VCC = 3.15V VCC = Min to Max (Note 8) VCC = 3.15V VOL C Port VCC = Min to Max (Note 8) VCC = 3.15V B Port II Control Pins and A Port B Port IOFF VCC = 3.45V VCC = 3.15V VCC = 3.45V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24mA IOL = 100 A IOL = 8 mA IOL = 24 mA IOL = 40 mA IOL = 50 mA VI = 3.45V VI = 0V VI = VTT VI = 0 A or C Ports, VCC = 0 Control Pins B Port II (HOLD) IOZH IOZL IPU/PD A Port C Port B Port C Port B Port All Ports VCC = 0 to 1.5V VCC = 3.45V VCC = 0 VCC = 3.15V VCC = 3.45V VI or VO = 0 to 1.5V VI = 0.8V VI = 2.0V VO = 3.45V VO = 1.5V VO = 0V VO = 0.55V VI = 0 to 3.45V 75 -75 10 5 -10 -5 30 30 A VI or VO = 0 to 3.45V VCC -0.2 2.4 2.2 0.2 0.4 0.5 0.4 0.5 10 -10 5 -5 30 V A A A V V 0.7 VREF + 50 mV 1.0 1.5 Test Conditions Min VREF + 0.05 2.0 0.0 VREF - 0.05 0.8 1.3 VCC -1.2 Typ (Note 7) VTT V V V V V Max Units
A A A A
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GTLP10B320
DC Electrical Characteristics
Symbol ICC A or B Ports or C Port ICC (Note 9) Ci A Port and Control Pins Control Pins and A Port C Port B Port
Note 7: All typical values are at VCC = 3.3V and TA = 25C.
(Continued)
Min Typ (Note 7) 27 27 27 45 45 45 2 4.5 6 9 pF mA mA Max Units
Test Conditions VCC = 3.45V IO = 0 VI = VCC/VTT or GND VCC = 3.45V, Outputs HIGH Outputs LOW Outputs Disabled One Input at VCC VI = VCC or 0 VI = VCC or 0 VI = VCC or 0
A or Control Inputs at VCC or GND -0.6V
Note 8: For conditions shown as Min, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50, but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX tWIDTH tSET Maximum Clock Frequency Pulse Duration Setup Time SAB = 0 SBC = 0 SAB = 1, SEL = 1, SBC = 0 SAB = 1, SEL = 0, SBC = 0 SAB = 1 SBC = 1 SAB = 1, SEL = 1, SBC = 1 SAB = 1, SEL = 0, SBC = 1 tHOLD Hold Time SAB = 0 SBC = 0 SAB = 1, SEL = 1, SBC = 0 SAB = 1, SEL = 0, SBC = 0 SAB = 1 SBC = 1 SAB = 1, SEL = 1, SBC = 1 SAB = 1, SEL = 0, SBC = 1 LECLKAB, LECLKBC HIGH or LOW A before LECLKAB B before LECLKBC A before LECLKBC A before LECLKBC A before LECLKAB B before LECLKBC A before LECLKBC A before LECLKBC A after LECLKAB B after LECLKBC A after LECLKBC A after LECLKBC A after LECLKAB B after LECLKBC A after LECLKBC A after LECLKBC Test Conditions Min 150 3.0 2.1 2.6 6.8 3.0 1.7 2.2 6.4 2.8 2.0 1.6 -1.4 1.4 2.5 2.1 -1.0 1.6 ns ns Max Unit MHz ns
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GTLP10B320
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = GND. CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol From (Input) An LECLKAB LECLKAB Bn To
Min 2.0 SAB = 1 1.1 2.2 SAB = 1 1.3 2.5 SAB = 0 1.4 1.4 SBC = 1 1.6 1.2 SBC = 1 1.5 1.3 SBC = 0 1.5 3.3 2.4 1.5 1.9 2.6 3.0 1.8 1.9 2.7 2.9 1.8 2.0
Typ (Note 10) 4.2 2.7 4.5 3.0 4.8 3.1 2.6 2.9 2.5 2.9 2.6 2.9 6.1 5.1 3.0 3.4 6.5 5.5 3.4 3.6 6.8 5.5 3.5 3.7 2.2 1.8 1.5 1.6
Max 7.5 4.9 6.7 5.6 7.1 5.7 4.4 5.0 4.5 5.0 4.6 5.0 10.3 8.0 5.4 5.8 9.5 8.6 6.0 6.3 10.0 8.6 6.3 6.5
Unit
(Output) Bn Bn Bn Cn
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPLH tPHL tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ
ns ns ns ns
LECLKBC LECLKBC An An LECLKAB LECLKAB LECLKAB LECLKAB
Cn Cn Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 0, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 0, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 0, SBC = 1 Cn SEL = 0, SAB = 0, SBC = 1
ns ns ns ns ns ns ns ns
Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (80% to 20%) Transition Time, C Outputs (10% to 90%) Transition Time, C Outputs (90% to 10%) SEL Cn 1.2 1.5 OEB Bn 1.1 2.0 OEC Cn 1.2 1.4
ns
2.8 2.8 2.8 4.3 2.9 2.8
4.9 5.3 5.2 8.9 5.3 4.9
ns
ns
ns
Note 10: All typical values are at VCC = 3.3V, and TA = 25C.
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GTLP10B320
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = GND. CL = 10 pF for B Port and CL = 10 pF for C Port.
Symbol From (Input) An LECLKAB LECLKAB Bn To
Min 1.6 SAB = 1 0.7 1.7 SAB = 1 0.9 2.0 SAB = 0 1.0 0.4 SBC = 1 0.6 0.2 SBC = 1 0.4 0.3 SBC = 0 0.4 2.1 1.0 0.5 0.8 1.1 1.4 0.8 0.9 1.2 1.3 0.9 0.9
Typ (Note 11) 3.9 2.4 4.1 2.7 4.4 2.7 1.8 2.2 1.8 2.0 1.8 2.1 5.1 4.1 2.3 2.6 5.3 4.3 2.6 2.8 5.6 4.3 2.8 2.9 2.0 1.8 0.6 0.7
Max 7.2 4.7 6.3 5.4 6.7 5.4 3.7 4.3 3.9 4.3 4.0 4.3 9.3 7.1 4.8 5.2 8.5 7.6 5.4 5.6 9.0 7.6 5.6 5.8
Unit
(Output) Bn Bn Bn Cn
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPLH tPHL tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ
ns ns ns ns
LECLKBC LECLKBC An An LECLKAB LECLKAB LECLKAB LECLKAB
Cn Cn Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 0, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 0, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 0, SBC = 1 Cn SEL = 0, SAB = 0, SBC = 1
ns ns ns ns ns ns ns ns
Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (80% to 20%) Transition Time, C Outputs (10% to 90%) Transition Time, C Outputs (90% to 10%) SEL Cn 0.3 0.4 OEB Bn 0.8 1.6 OEC Cn 0.6 0.6
ns
1.7 2.3 2.5 4.0 2.0 1.9
4.3 4.6 4.8 8.5 4.0 3.7
ns
ns
ns
Note 11: All typical values are at VCC = 3.3V, and TA = 25C.
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GTLP10B320
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = VCC. CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol From (Input) An LECLKAB LECLKAB An LECLKAB LECLKAB To
Min 1.2 SAB = 1 0.8 1.4 SAB = 1 1.0 1.6 SAB = 0 1.1 1.6 2.0 1.7 2.2 1.8 2.3
Typ (Note 12) 3.3 2.3 3.7 2.6 3.9 2.7 5.3 4.7 5.7 5.1 5.9 5.1 1.8 1.4
Max 7.3 4.5 6.0 5.1 6.3 5.2 8.1 7.5 8.8 8.1 9.1 8.2
Unit
(Output) Bn Bn Bn Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 0, SBC = 1
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPZH, tPZL tPHZ, tPLZ
ns ns ns ns ns ns ns
Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (80% to 20%) OEB Bn 0.5 1.7
2.4 3.4
4.7 5.9
ns
Note 12: All typical values are at VCC = 3.3V, and TA = 25C.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = VCC. CL = 10 pF for B Port and CL = 10 pF for C Port.
Symbol From (Input) An LECLKAB LECLKAB An LECLKAB LECLKAB To
Min 0.8 SAB = 1 0.5 0.6 SAB = 1 0.6 0.8 SAB = 0 0.7 0.2 0.6 0.2 0.7 0.3 0.8
Typ (Note 13) 3.0 2.1 3.2 2.3 3.5 2.4 4.2 3.7 4.5 3.9 4.8 3.9 1.4 1.2
Max 7.0 4.3 5.7 4.8 6.0 4.9 8.1 6.6 7.7 7.2 8.0 7.2
Unit
(Output) Bn Bn Bn Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 1, SBC = 1 Cn SEL = 1, SAB = 0, SBC = 1
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPZH, tPZL tPHZ, tPLZ
ns ns ns ns ns ns ns
Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (80% to 20%) OEB Bn 0.2 1.3
2.1 3.0
4.4 5.5
ns
Note 13: All typical values are at VCC = 3.3V, and TA = 25C.
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GTLP10B320
AC Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free air temperature VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol Path A A
From Bn Bn Bn Bn Bn Bn Cn Cn Cn Cn Cn Cn Cn Cn Cn Cn
To B(n+1) B(n+1) B(n+1) B(n+1) B(n+1) B(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1) C(n+1)
Mode SAB = 1 SAB = 1 SAB = 1 SAB = 1 SAB = 0 SAB = 0 SBC = 1 SBC = 1 SBC = 1 SBC = 1 SBC = 1 SBC = 1 SBC = 0 SBC = 0 SBC = 0
Max 0.5 0.4 2.0 0.5 0.4 2.0 0.5 0.4 2.0 0.4 0.4 1.0 1.5 0.4 0.4 1.0 1.5 0.4 0.4 1.0 1.5 0.4 0.4
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tOSLH (Note 14) tOSHL (Note 14) tPVHL (Note 15)(Note 16) tOSLH (Note 14) tOSHL (Note 14) tPVHL (Note 15)(Note 16) tOSLH (Note 14) tOSHL (Note 14) tPVHL (Note 14)(Note 15) tOSLH (Note 14) tOSHL (Note 14) tOST (Note 14) tPV (Note 15) tOSLH (Note 14) tOSHL (Note 14) tOST (Note 14) tPV (Note 15) tOSLH (Note 14) tOSHL (Note 14) tOST (Note 14) tPV (Note 15) tOSLH (Note 14) tOSHL (Note 14) tOST (Note 14) tPV (Note 15)
LECLKAB LECLKAB LECLKAB LECLKAB B B B LECLKBC LECLKBC LECLKBC LECLKBC LECLKBC LECLKBC SEL
SEL SEL
Cn Cn
C(n+1) C(n+1)
1.0 1.2
Note 14: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 15: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 16: Due to the open drain structure on GTLP outputs tOST and t PV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane.
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GTLP10B320
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
Test tPLZ/tPZL
S 6V
tPLH/tPHL Open tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance. Note B: For B Port, CL = 30 pF or 10 pF.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output.
Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY VCC 0.0 VCC/2 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50 The outputs are measured one at a time with one transition per measurement.
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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 12 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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